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Here, we present a temperature ($T$) dependent comparison betweenfield-effect and Hall mobilities in field-effect transistors based onfew-layered WSe$_2$ exfoliated onto SiO$_2$. Without dielectric engineering andbeyond a $T$-dependent threshold gate-voltage, we observe maximum holemobilities approaching 350 cm$^2$/Vs at $T$=300 K. The hole Hall mobilityreaches a maximum value of 650 cm$^2$/Vs as $T$ is lowered below $\sim$ 150 K,indicating that insofar WSe$_2$-based field-effect transistors (FETs) displaythe largest Hall mobilities among the transition metal dichalcogenides. Thegate capacitance, as extracted from the Hall-effect, reveals the presence ofspurious charges in the channel, while the two-terminal sheet resistivitydisplays two-dimensional variable-range hopping behavior, indicating carrierlocalization induced by disorder at the interface between WSe$_2$ and SiO$_2$.We argue that improvements in the fabrication protocols as, for example, theuse of a substrate free of dangling bonds are likely to produce WSe$_2$-basedFETs displaying higher room temperature mobilities, i.e. approaching those of$p$-doped Si, which would make it a suitable candidate for high performanceopto-electronics.

Hall and field-effect mobilities in few layered $p$-WSe$_2$ field-effect transistors