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3D monolithic integration of logic and memory has been the most sought after solution to surpass the Von Neumann bottleneck, for which a low-temperature processed material system becomes inevitable. Two-dimensional materials, with their excellent electrical properties and low thermal budget are potential candidates. Here, we demonstrate a low-temperature hybrid co-integration of one-transistor-one-resistor memory cell, comprising a surface functionalized 2D WSe 2   p- FET, with a solution-processed WSe 2  Resistive Random Access Memory. The employed plasma oxidation technique results in a low Schottky barrier height of 25 meV with a mobility of 230 cm 2  V −1  s −1 , leading to a 100x performance enhanced WSe 2   p -FET, while the defective WSe 2  Resistive Random Access Memory exhibits a switching energy of 2.6 pJ per bit. Furthermore, guided by our device-circuit modelling, we propose vertically stacked channel FETs for high-density sub-0.01 μm 2  memory cells, offering a new beyond-Si solution to enable 3-D embedded memories for future computing systems.

All WSe2 1T1R resistive RAM cell for future monolithic 3D embedded memory integration