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Wafer-scale fabrication of semiconductor nanowire devices is readily facilitated by lithography-based top-down fabrication of polysilicon nanowire (P-SiNW) arrays. However, free carrier trapping at the grain boundaries of polycrystalline materials drastically changes their properties. We present here transport measurements of P-SiNW array devices coupled with Kelvin probe force microscopy at different applied biases. By fitting the measured P-SiNW surface potential using electrostatic simulations, we extract the longitudinal dopant distribution along the nanowires as well as the density of grain boundaries interface states and their energy distribution within the band gap.

Density and Energy Distribution of Interface States in the Grain Boundaries of Polysilicon Nanowire