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The performance and reliability of Ultra-Low-Power (ULP) computing platformsare adversely affected by environmental temperature and process variations.Mitigating the effect of these phenomena becomes crucial when these devicesoperate near-threshold, due to the magnification of process variations and tothe strong temperature inversion effect that affects advanced technology nodesin low-voltage corners, which causes huge overhead due to margining for timingclosure. Supporting an extended range of reverse and forward body-bias, UTBBFD-SOI technology provides a powerful knob to compensate for such variations.In this work we propose a methodology to maximize energy efficiency at run-timeexploiting body biasing on a ULP platform operating near-threshold. Theproposed method relies on on-line performance measurements by means of ProcessMonitoring Blocks (PMBs) coupled with an on-chip low-power body bias generator.We correlate the measurement performed by the PMBs to the maximum achievablefrequency of the system, deriving a predictive model able to estimate it withan error of 9.7% at 0.7V. To minimize the effect of process variations wepropose a calibration procedure that allows to use a PMB model affected by onlythe temperature-induced error, which reduces the frequency estimation error by2.4x (from 9.7% to 4%). We finally propose a controller architecture relying onthe derived models to automatically regulate at run-time the body bias voltage.We demonstrate that adjusting the body bias voltage against environmentaltemperature variations leads up to 2X reduction in the leakage power and a 15%improvement on the global energy consumption when the system operates at 0.7Vand 170MHz

Performance-Aware Predictive-Model-Based On-Chip Body-Bias Regulation Strategy for an ULP Multi-Core Cluster in 28nm UTBB FD-SOI