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Bi-directional motion search is one of the important features of B picture coding in H.264/AVC. However, its high computational complexity and huge memory traffic make design difficult. This paper proposes a high throughput and cost efficient VLSI architecture for bi-directional integer motion estimation (Bi-IME). The redundancy of the joint motion search is removed, and the algorithm is simplified. Novel memory structure and intelligent reading method are designed to satisfy the iterations of full search with two reference windows. The parallel and sequence techniques are adopted to process the matching procedure. After logic synthesis using SMIC 0.13 μm standard cell library, under a clock frequency of 300 MHz, the proposed Bi-IME architecture can provide processing capacity up to 149 M MBs/sec which is enough for 1080p real-time video systems

High Performance VLSI Architecture of Bi-directional Motion Search for B Picture in H.264