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As the complexity of semiconductors grows rapidly, the volume of test data for them also increases enormously. Multi-Valued Logic(MVL) is one of solutions to meet test economics. MVL-based ATE can transmit several test data bits concurrently in a line, because MVL can have more than two values. Thus, even if the test clock speed is the same as DUT's, the test data can be expanded in proportional to the MVL bit steps. Moreover, the test accessories like a socket is easy to make due to lower test clock than binary TAM's one and the power consumption will be smaller too.However, MVL interface is vulnerable to noise for the small noise margin and needs decoders to convert MVL to binary data. In this paper, we simulate previous quaternary decoders if they are suitable for MVL decoder. After the simulation, an efficient decoder structure for MVL interface is proposed to improve the performance as well as the size

MVL-based Test Access Mechanism for Big Data Interface