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We present a multi-layer single-event upset mitigation strategy implementedin a low-cost Xilinx Artix-7 FPGA. The implementation is targeted for a triggerdata router for the ATLAS muon spectrometer upgrade. The mitigation strategyemploys three layers of protection to improve overall FPGA design robustness:use of triple-modular redundancy for FPGA fabric logic and embedded soft-errormitigation in the first layer; further enhancement with multi-boot FPGAreconfiguration across multiple copies of configuration memory in the secondlayer; and FPGA power cycling and configuration memory re-initialization in thethird layer. The effectiveness of this scheme has been evaluated at twodifferent neutron facilities, LANSCE and NCSR Demokritos, with 800 MeV and 25MeV beam energies, respectively. Testing was performed with a similarconfiguration to that planned for final operation. We discuss the testingstrategy and summarize the test results to estimate the expected data loss over10 years of operation in the ATLAS experiment.

A Multi-Layer SEU Mitigation Strategy to Improve FPGA Design Robustness for the ATLAS Muon Spectrometer Upgrade