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The assessment of noise margins and the related probability of failure indigital cells has growingly become essential, as nano-scale CMOS and FinFETtechnologies are confronting reliability issues caused by aging mechanisms,such as NBTI, and variability in process parameters. The influence of suchphenomena is particularly associated to the Write Noise Margins (WNM) in memoryelements, since a wrong stored logic value can result in an upset of the systemstate. In this work, we calculated and compared the effect of processvariations and NBTI aging over the years on the actual WNM of various CMOS andFinFET based flip-flop cells. The massive transistor-level Monte Carlosimulations produced both nominal (i.e. mean) values and associated standarddeviations of the WNM of the chosen flip-flops. This allowed calculating theconsequent write failure probability as a function of an input voltage shift onthe flip-flop cells, and assessing a comparison for robustness among differentcircuit topologies and technologies.

Effect of NBTI/PBTI Aging and Process Variations on Write Failures in MOSFET and FinFET Flip-Flops