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Vertical organic field-effect transistors (VOFETs) provide an advantage over lateral ones with respect to the possibility to conveniently reduce the channel length. This is beneficial for increasing both the cut-off frequency and current density in organic field-effect transistor devices. We prepared P3HT (poly[3-hexylthiophene-2,5-diyl]) VOFETs with a surrounding gate electrode and gate dielectric around the vertical P3HT pillar junction. Measured output and transfer characteristics do not show a distinct gate effect, in contrast to device simulations. By introducing in the simulations an edge layer with a strongly reduced charge mobility, the gate effect is significantly reduced. We therefore propose that a damaged layer at the P3HT/dielectric interface could be the reason for the strong suppression of the gate effect. We also simulated how the gate effect depends on the device parameters. A smaller pillar diameter and a larger gate electrode-dielectric overlap both lead to better gate control. Our findings thus provide important design parameters for future VOFETs

Fabrication, electrical characterization and device simulation of vertical P3HT field-effect transistors