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We describe the hardwired implementation of algorithms for Monte Carlosimulations of a large class of spin models. We have implemented thesealgorithms as VHDL codes and we have mapped them onto a dedicated processorbased on a large FPGA device. The measured performance on one such processor iscomparable to O(100) carefully programmed high-end PCs: it turns out to be evenbetter for some selected spin models. We describe here codes that we arecurrently executing on the IANUS massively parallel FPGA-based system.

Simulating spin systems on IANUS, an FPGA-based computer