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The success of memory technology is of vital importance in order to handle emerging mass amount of data in our daily lives. Let us take one example here: The IBM summit is the supercomputer released in 2018 and it plays an important role to help researchers run large numbers of calculations and better understand COVID-191). To enable such powerful computing capability, the IBM summit includes 250 petabytes storage capacity2) . To make a fair comparison, this is larger than the total number of all the ants we can find on the earth (on the order of 1016–1017)3). Unfortunately, the performance of the memory chips still has so much room for improvement because of the big performance gap between the dynamic-random-access-memory (DRAM) and the flash memory. DRAM is volatile and the stored charge in a DRAM cell will gradually leak out, requiring periodic refresh operation that causes significant power consumption. In contrast, flash memories are suffering from slow access speed and limited endurance characteristics. As such, the performance of chips would be further improved by including the storage class memory (SCM) into the state-of-the-art memory hierarchy and bridge the performance gap between DRAM and Flash memory [1]. Among different non-volatile memory candidates [2, 3], the phase change memory (PCM) technology is considered as one of the most suitable SCM options, which offers reasonable switching speed (between the ones from DRAM and Flash memory), non-volatility, robust endurance and high density [1].

Multi level cell (MLC) in 3D crosspoint phase change memory array