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Today, hard real-time systems are found inmanydiverse application areas including; autonomous vehicles, avionics, space systems, and robotics. In these areas, technological progress is resulting in rapid increases in both software complexity and processing demands. To address these requirements, silicon vendors have shifted their focus from single-core to multicore hardware platforms. Multicore hardware integrates multiple processing cores onto a single chip. To reduce costs and to improve performance in the average case, these cores typically share a number of hardware resources; including parts of thememory hierarchy such as the last level cache (LLC), main memory (DRAM), and the interconnect. By contending for these shared hardware resources, tasks executing on one core can potentially interfere with tasks executing on another core, increasing their worst-case execution times. Contention for shared resources thus poses a significant challenge in the development of real-time systems. In some cases the contention is so great that the analysable, guaranteed real-time performance may be no better than that for a single core. With the adoption of multicore technology comes the opportunity to combine different applications on the same hardware platform, reducing size, weight and power consumption, as well as assembly and production costs for the overall system. Here, different applications may have different criticality levels, designating the level of assurance needed against failure. For example, in an avionics context, flight control and surveillance applications in unmanned aerial vehicles (UAVs) are of high and low criticality respectively. The problem of combining high and low criticality applications on the same hardware platform raises issues of how to reconcile the conflicting

Guest editorial: special issue on mixed-criticality, multi-core, and micro-kernels