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The Network-on-Chip (NoC) paradigm has been proposed as a favorable solutionto handle the strict communication requirements between the increasingly largenumber of cores on a single chip. However, NoC systems are exposed to theaggressive scaling down of transistors, low operating voltages, and highintegration and power densities, making them vulnerable to permanent (hard)faults and transient (soft) errors. A hard fault in a NoC can lead to externalblocking, causing congestion across the whole network. A soft error is morechallenging because of its silent data corruption, which leads to a large areaof erroneous data due to error propagation, packet re-transmission, anddeadlock. In this paper, we present the architecture and design of acomprehensive soft error and hard fault-tolerant 3D-NoC system, named3D-Hard-Fault-Soft-Error-Tolerant-OASIS-NoC (3D-FETO). With the aid ofefficient mechanisms and algorithms, 3D-FETO is capable of detecting andrecovering from soft errors which occur in the routing pipeline stages andleverages reconfigurable components to handle permanent faults in links, inputbuffers, and crossbars. In-depth evaluation results show that the 3D-FETOsystem is able to work around different kinds of hard faults and soft errors,ensuring graceful performance degradation, while minimizing additional hardwarecomplexity and remaining power efficient.

A low-overhead soft-hard fault-tolerant architecture, design and management scheme for reliable high-performance many-core 3D-NoC systems