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Scalability from single-qubit operations to multi-qubit circuits for quantum information processing requires architecture-specific implementations. Semiconductor hybrid qubit architecture is a suitable candidate to realize large-scale quantum information processing, as it combines a universal set of logic gates with fast and all-electrical manipulation of qubits. We propose an implementation of hybrid qubits, based on Si metal-oxide-semiconductor (MOS) quantum dots, compatible with the CMOS industrial technological standards. We discuss the realization of multi-qubit circuits capable of fault-tolerant computation and quantum error correction, by evaluating the time and space resources needed for their implementation. As a result, the maximum density of quantum information is extracted from a circuit including eight logical qubits encoded by the [[7, 1, 3]] Steane code. The corresponding surface density of logical qubits is 2.6 Mqubit/cm.

Maximum density of quantum information in a scalable CMOS implementation of the hybrid qubit architecture