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Programmable logic controller (PLC) is one of the most important components in today’s manufacturing. Its performance-based microprocessor and software have been a bottleneck for improving its efficiency. To enhance the PLC performance and flexibility, a new PLC design based on field programmable gate array (FPGA) has been a hot topic because of its parallel execution mechanism and reconfigurable hardware structure. From practical viewpoint, in this paper, the authors propose an approach to implement the existing ladder diagram (LD) inside FPGA making full use of the advantage of FPGA device. The essential of this research includes two issues: (a) analyze the LD program and organize it with sequential and parallel structure and (b) implement the sequential and parallel structure of the LD program with hardware description language inside FPGA. To the first work, the condensed simultaneity graph theory is applied to optimize the LD program with sequential and parallel structure. To the second work, Boolean equations are taken as the bridge to convert the optimized LD program to the hardware description language program. Finite state machine is used to generate sensitive signals to guarantee that the performance of the converted very high-speed integrated circuit hardware description language design is the same as the original ladder diagram. A case study is practiced to verify the proposed approach in this paper.

A study on the generation of silicon-based hardware Plc by means of the direct conversion of the ladder diagram to circuit design language