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We model the shared buffer ATM switch as a discrete-time queueing system. The arrival process to each port of the ATM switch is assumed to be bursty and it is modelled by an interrupted Bernoulli process. The discrete-time queueing system is analyzed approximately. It is first decomposed into subsystems, and then each subsystem is analyzed separately. The results from the subsystems are combined together through an iterative scheme. The analysis of each subsystem involves the construction of the superposition of all the arrival processes to the switch. Comparisons with simulation data showed that the approximate results have a good accuracy.

A discrete-time queueing model of the shared buffer ATM switch with bursty arrivals