VLSI Design and Test

The modern real time embedded applications are implemented as a mixture software-hardware designs. In the most of the hardware-software codesigns, the main processor is used to perform the part of the operation in software and to send/retrieve data to/from the hardware or co-processor. This paper proposes efficient hardware-software codesigns for AES encryptor and RS-BCH concatenated encoder, where the latency and hardware cost lie in between the fully hardware and software based designs. The synthesis results show that our proposed hardware-software codesigns of 128-bit AES and RS(255,239)-BCH(2184,2040) serial concatenated error correction encoder achieve 85% and 40% of reduction in switching power dissipation over the conventional folded AES design and [8] using Artix-7 FPGA implementation respectively.