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While FPGA and other reconfigurable technologies have dramatically increased in size and speed, memory technology has had only modest improvements. Relative to logic speeds, memory latency is virtually flat and physical constraints on external pins limit memory bandwidth. Unfortunately, the traditional cache hierarchy found in fixedfunction integrated circuits has evolved to support sequential processors and is ineffective for highly parallel architectures. This paper proposes a novel memory subsystem and computational model for reconfigurable architectures.

A Novel Memory Subsystem and Computational Model for Parallel Reconfigurable Architectures