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International audienceFor mobile devices, this paper proposes a compacthardware (H/W) implementation for the KASUMI block cipher, which is the3GPP standard encryption algorithm. In [4], Yamamoto et al. proposed themethod of reducing temporary registers for the MISTY1 FO function(YYI-08), and implemented a very compact MISTY1 H/W. This paper aims todesign the smallest KASUMI H/W by the application of YYI-08 to KASUMI,which has a similarly structured MISTY1 FO function. We discussed theapplicability and found the problems on register competition and logicalequivalence in the simple application, so we propose the new YYI-08improved for KASUMI and the compact H/W architecture. According to ourlogic synthesis on a 0.11-μm ASIC process, the gate size is 2.99 Kgates,which is the smallest as far as we know

A Very Compact Hardware Implementation of the KASUMI Block Cipher