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International audienceNetwork-on-Chip (NoC) has emerged as a verypromising paradigm for designing scalable communication architecture forSystems-on-Chips (SoCs). However, NoCs designed to fulfill the bandwidthrequirements between the cores of an SoC for a certain set of runningapplications may be highly sub-optimal for another set of applications.In this context, methods that can lead to versatility enhancements ofinitial NoC designs to changing working conditions, imposed by variablesets of executed real-life applications at each moment in time, are veryimportant for designing competitive NoCs in industrial SoCs. In thiswork, we present a run-time reconfigurable NoC framework based on thepartial dynamic reconfiguration capabilities of Field-Programmable GateArrays (FPGAs). This new NoC framework can dynamically create/deleteexpress lines between SoC components (implementing dynamicallycircuit-switching channels) and perform run-time NoC topology androuting-table reconfigurations to handle interconnection congestion,with a very limited performance overhead. Moreover, we show in ourexperimental results that the addition of these dynamic reconfigurationcapabilities into basic NoCs using our framework only implies a verylimited area overhead (around 10% on average) with respect to theinitial NoC designs; thus, it can bring great benefits when compared totraditional non-reconfigurable NoC design approaches for worst-casebandwidth requirements in SoCs with many possible sets of runningapplications

A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication