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International audienceIn current reconfigurable architectures, theinterconnect structures increasingly contribute to the delay and powerconsumption budget. The demand for increased clock frequencies and logicavailability (smaller area foot print) makes the problem even moreimportant, leading among others to rapid elevation in power density.Three-dimensional (3D) architectures are able to alleviate this problemby accommodating a number of functional layers, each of which might befabricated in different technology. Since power consumption is acritical challenge for implementing applications onto reconfigurablehardware, a novel temperature-aware placement and routing (P&R)algorithm targeting 3D FPGAs, is introduced. The proposed algorithmachieves to redistribute the switched capacitance over identicalhardware resources in a rather "balanced" profile, reducing among othersthe number of hotspot regions, the maximal values of power sources athotspots, as well as the percentage of device area that consumes highpower. For evaluation purposes, the proposed approach is realized as anew CAD tool, named 3DPRO (3D-Placement-and-Routing-Optimization), whichis part of the complete framework, named 3D MEANDER. Comparing toalternative solutions, the proposed one reduces the percentage ofsilicon area that operates under high power by 63%, while it leads toenergy savings (about 9%), with an almost negligible penalty inapplication's delay ranging from 1% up to 5%

A Temperature-Aware Placement and Routing Algorithm Targeting 3D FPGAs