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A recent model for testing systems with multiple timers is extended to compute proper input delays and timeout settings, and is applied to several types of timers required in a testing procedure. In the model, any transition in the specication can be made conditional on a set of running timers. Depending on the path taken to reach an edge, the values of the timer variables may render the traversal of the edge infeasible. The presented modeling technique, combined with the INcon- sistencies DEtection and ELimination (INDEEL) algorithms, allows the generation of feasible test sequences. The model also oers the exibil- ity to dene timer lengths as variables, and have the INDEEL nd the

Towards Testing SDL Specifications: Models and Fault Coverage for Concurrent Timers