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Power dissipation has recently emerged as one of the most critical design constraints. A wide range of techniques has already been proposed for the optimization of logic circuits for low power. Power management methods are among the most effective techniques for power reduction. These methods detect periods of time during which parts of the circuit are not doing useful work and shut them down by either turning off the power supply or the clock signal. In this work, we describe the integration of dynamic power management tools in a design flo w. The designer can thus easily apply these techniques to the design, evaluate the optimization achieved and decide if the changes are worthwhile to include in the finaldesign. We have used this design flo w with a real project. An HDLC controller has been designed and these power management techniques have been applied.

Integrating Dynamic Power Management in the Design Flow