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We present a combined architectural and circuit technique for reducing the en- ergy dissipation of microprocessor memory structures. Thi s approach exploits the subarray partitioning of high speed memories and varying application re- quirements to dynamically disable partitions during appro priate execution peri- ods. When applied to 4-way set associative caches, trading off a 2% performance degradation yields a combined 40% reduction in L1 Dcache and L2 cache energy dissipation.

An Architectural and Circuit-Level Approach to Improving the Energy Efficiency of Microprocessor Memory Structures