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Exponentially increasing with technology scaling, soft er rors have become a serious design concern in the deep sub-micron embedded systems. Partially Protected Cache (PPC) is a promising microarchitectural feature to mitigate fail- ures due to soft errors in embedded processors. A processor with PPC maintains two caches, one protected and the other unprotected, both at the same level of memory hierarchy. The intuition behind PPC is that some data in the application is more prone to soft errors than others. By finding out the dat a more prone to soft errors and mapping only that to the protected cache, the failure rate can be significantly impro ved at minimal power and performance penalty. While the ef- fectiveness of PPCs has been demonstrated on multimedia applications - where the multimedia data is inherently resilie nt to soft errors - no such obvious data partitioning exists for applications in general. This severely restricts the appli cability of PPCs. This paper proposes profile-based data partitionin g schemes that are applicable to applications in general and effectively reduce failures due to soft errors at minimal power and performance overheads. Our experimental results on HP iPAQ-like processor and memory configuration demonstrate t hat our algorithm efficiently reduces the failure rate by 47 × on benchmarks from MiBench while incurring only 0.5% performance and 15% power overheads.

Data Partitioning Techniques for Partially Protected Caches to Reduce Soft Error Induced Failures