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State Machines.The MDG tools are intended for Abstract State Machines (ASM) verification[4, 3] rather than Finite State Machine (FSM) verification. They can be usedfor FSMs as well, but they are less efficient than ROBDDs for this purpose,due in part to the space requirements of our current Prolog implementation.An abstract description of a state machine, called abstract state machine(ASM) [4], is obtained by letting some data input, state or output variablesbe of an abstract sort,...

MDG tools for the verification of RTL designs