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Firstly, we show how to deal with bounded uncertain delays of (speed-dependent) asynchronous circuits for symbolic model checking based on temporal logic. We adopt discrete-time model. In the modeling of uncertain delays, we consider two models, i.e. static delay and dynamic delay. These models are interpreted as parameterized sequential machines and nondeterministic sequential machines respecitively.

Formal verification of speed-dependent asynchronous circuits using symbolic model checking of Branching Time Regular Temporal Logic