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This paper presents integer multiplication and division operators dedicated to Virtex-II FPGAs from Xilinx. Those operators are based on small 18脳18 multiplier blocks available in the Virtex-II device family. Various trade-offs are explored (computation decomposition, radix, digit sets . . . ) using specific VHDL generators. The obtained op-eratorslead to speed improvements up to 18% for multiplication and 40% for division compared to standard solutions only based on CLBs.

Small Multiplier-Based Multiplication and Division Operators for Virtex-II Devices