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The performance of linear relaxation codes strongly depends on an efficient usage of caches. This paper considers one time step of the Jacobi and Gau脽-Seidel kernels on a 3D array, and shows that tiling reduces the number of capacity misses to almost optimum. In particular, we prove that 驴(N3/(L驴C)) capacity misses are needed for array size N 脳 N 脳 N, cache size C, and line size L. If cold misses are taken into account, tiling is off the lower bound by a factor of about 1+5/驴LC. The exact value depends on tile size and data layout. We show analytically that rectangular tiles of shape (N-2) 脳 s 脳 (sL/2) outperform square tiles, for row-major storage order.

Tight Bounds on Capacity Misses for 3D Stencil Codes