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Various approaches to buffer size and management for output buffering in ATM switches supporting delay sensitive traffic are reviewed. Discrete worst case arrival and service functions are presented. Using this format, bounds are developed for buffer size under zero cell loss for leaky bucket constrained sources. Tight bounds are developed for the case of discrete arrival functions with fluid servers and fluid arrival functions with discrete servers. A bound on the buffer size is also proposed for the case of discrete arrival and service process. While this bound is not exact, the maximum gain that could be achieved by a tighter bound is bounded. In some cases it is possible to reduce the buffer size requirements through over allocation of link bandwidth. Feasibility conditions for this scenario are developed.

Buffer Size Requirements for Delay Sensitive Traffic Considering Discrete Effects and Service-Latency in ATM Switches