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This communication shows the influence of clocking schemes on the digital switching noise generation. It will be shown how the choice of a suited clocking scheme for the digital part reduces the switching noise, thus alleviating the problematic associated to limitations of performances in mixed-signal Analog/Digital Integrated Circuits. Simulation data of a pipelined XOR chain using both a single-phase and a two-phase clocking schemes, as well as of two n-bit counters with different clocking styles lead, as conclusions, to recommend multiple clock-phase and asynchronous styles for reducing switching noise.

Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits