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Side channel attacks can be effectively a ddressed at the circuit level by using dynamic differential logic styles. A key problem is to guarantee a balanced ca- pacitive load at the differential outputs of the lo gic gates. The main contribu- tion to this load is the capacitance associated wit h the routing between cells. This paper describes a novel design methodology to route a design in which multiple differential pairs are present. The method ology is able to route 20K+ differential routes. The differential routes are al ways routed in adjacent tracks and the parasitic effects between the two wires of each differential pair are balanced. The methodology is developed on top of a commercially available EDA tool. It has been developed as part of a secure digital design flow to pro- tect security applications against Differential Pow er Analysis attacks. Experi- mental results indicate that a perfect protection i s attainable with the aid of the proposed differential routing strategy.

Place and Route for Secure Standard Cell Design