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Pass-transistor logic SPL has been introduced as a circuit structure to achieve lower power consumption of LSI, and its effectiveness has been confirmed. In the current study, the authors discuss a test generation method for using logic tests to detect stuck-on faults of pass transistors in SPL. First, the authors discuss a technique for generating a logic discrepancy (D or D) between a normal circuit and a faulty circuit in an SPL circuit, and a test generation procedure using this technique. Next, they discuss a technique to solve the problem of size explosion of a table, prepared in advance for this technique in order to obtain logic values in faulty circuits. Then, the authors propose DFT (design for testability) circuits featuring very low chip surface overhead and speed overhead, to improve the fault coverage. Finally, to demonstrate its effectiveness, the method was applied to benchmark circuits. © 1999 Scripta Technica, Syst Comp Jpn, 30(7): 5568, 1999

Test generation for stuck-on faults in pass-transistor logic SPL and implementation of DFT circuits