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This paper presents SIRENA, a CAD environment for the simulation and modeling of mixed-signal VLSI parallel processing chips based on Cellular Neural Networks. SIRENA includes capabilities for: a) the description of nominal and non-ideal operation of CNN analog circuitry at the behavioral level; b) performing realistic simulations of the transient evolution of physical CNNs including deviations due to second-order effects of the hardware; and, c) evaluating sensitivity figures, and realize noise and Montecarlo simulations in the time domain. These capabilities portray SIRENA as better suited for CNN chip development than algorithmic simulation packages (such as OpenSimulator, Sesame) or conventional Neural Networks simulators (RCS, GENESIS, SFINX), which are not oriented to the evaluation of hardware non-idealities. As compared to conventional electrical simulators (such as HSPICE or ELDO-FAS), SIRENA provides easier modeling of the hardware parasitics, a significant reduction in computation time, and similar accuracy levels. Consequently, iteration during the design procedure becomes possible, supporting decision making regarding design strategies and dimensioning. SIRENA has been developed using object-oriented programming techniques in C, and currently runs under the UNIX operating system and X-Windows framework. It employs a dedicated high-level hardware description language: DECEL, fitted to the description of non-idealities arising in CNN hardware. This language has been developed aiming generality, in the sense of making no restrictions on the network models that can be implemented. SIRENA is highly modular andcomposed of independent tools. This simplifies future expansions and improvements. Front-page Footnotes: 1 2 1. This work has been partially funded by spanish CICYT under contract TIC96-1392-C02-02 (SIVA). 2. Research of Ricardo Carmona has been partially supported by IBERDROLA, S. A. under contract INDES-94/377 SIRENA: A CAD Environment for Behavioral Modeling and Simulation of VLSI Cellular Neural Network Chips 2 SIRENA: A CAD Environment for Behavioral Modeling and Simulation of VLSI Cellular Neural Network Chips R. Carmona, I. García-Vargas, G. Liñán, R. Domínguez-Castro, S. Espejo and A. RodríguezVázquez

SIRENA: A CAD environment for behavioural modelling and simulation of VLSI cellular neural network chips