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The balance metric is a simple approach to estimate the performance ofbandwidth-limited loop kernels. However, applying the method to in-cachesituations and modern multi-core architectures yields unsatisfactory results.This paper analyzes the in uence of cache hierarchy design on performancepredictions for bandwidth-limited loop kernels on current mainstreamprocessors. We present a diagnostic model with improved predictive power,correcting the limitations of the simple balance metric. The importance of codeexecution overhead even in bandwidth-bound situations is emphasized. Finally weanalyze the impact of synchronization overhead on multi-threaded performancewith a special emphasis on the in uence of cache topology.

Multi-core architectures: Complexities of performance prediction and the impact of cache topology