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This paper addresses efficient hardware/software implementation approachesfor the AES (Advanced Encryption Standard) algorithm and describes the designand performance testing algorithm for embedded system. Also, with the spread ofreconfigurable hardware such as FPGAs (Field Programmable Gate Array) embeddedcryptographic hardware became cost-effective. Nevertheless, it is worthy tonote that nowadays, even hardwired cryptographic algorithms are not so safe.  From another side, the self-reconfiguring platform is reported that enablesan FPGA to dynamically reconfigure itself under the control of an embeddedmicroprocessor. Hardware acceleration significantly increases the performanceof embedded systems built on programmable logic. Allowing a FPGA-basedMicroBlaze processor to self-select the coprocessors uses can help reduce arearequirements and increase a system's versatility. The architecture proposed inthis paper is an optimal hardware implementation algorithm and takes dynamicpartially reconfigurable of FPGA. This implementation is good solution topreserve confidentiality and accessibility to the information in the numericcommunication.

Self-Partial and Dynamic Reconfiguration Implementation for AES using FPGA