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In the nano era in integrated circuit fabrication technologies, theperformance variability due to statistical process and circuit parametervariations is becoming more and more significant. Considerable effort has beenexpended in the EDA community during the past several years in trying to copewith the so-called statistical timing problem. Most of this effort has beenaimed at generalizing the static timing analyzers to the statistical case. Inthis paper, we take a pragmatic approach in pursuit of making the Monte Carlomethod for timing yield estimation practically feasible. The Monte Carlo methodis widely used as a golden reference in assessing the accuracy of other timingyield estimation techniques. However, it is generally believed that it can notbe used in practice for estimating timing yield as it requires too many costlyfull circuit simulations for acceptable accuracy. In this paper, we present anovel approach to constructing an improvedMonte Carlo estimator for timingyield which provides the same accuracy as the standard Monte Carlo estimator,but at a cost of much fewer full circuit simulations. This improved estimatoris based on a novel combination of a variance reduction technique, importancesampling, and a stochastic generalization of the logical effort formalism forcheap but approximate delay estimation. The results we present demonstrate thatour improved yield estimator achieves the same accuracy as the standard MonteCarlo estimator at a cost reduction reaching several orders of magnitude.

Fast Monte Carlo Estimation of Timing Yield: Importance Sampling with Stochastic Logical Effort (ISLE)