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This paper presents a BPD (Balanced Power Dissipation) heuristic schedulingalgorithm applied to VLSI CMOS digital circuits/systems in order to reduce theglobal computational demand and provide balanced power dissipation ofcomputational units of the designed digital VLSI CMOS system during the taskassignment stage. It results in reduction of the average and peak temperaturesof VLSI CMOS digital circuits. The elaborated algorithm is based on balancedpower dissipation of local computational (processing) units and does notdeteriorate the throughput of the whole VLSI CMOS digital system.

Reducing Average and Peak Temperatures of VLSI CMOS Digital Circuits by Means of Heuristic Scheduling Algorithm