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IEEE 754r is the ongoing revision to the IEEE 754 floating point standard anda major enhancement to the standard is the addition of decimal format.Furthermore, in the recent years reversible logic has emerged as a promisingcomputing paradigm having its applications in low power CMOS, quantumcomputing, nanotechnology, and optical computing. The major goal in reversiblelogic is to minimize the number of reversible gates and garbage outputs. Thus,this paper proposes the novel concept of partial reversible gates that willsatisfy the reversibility criteria for specific cases in BCD arithmetic. Thepartial reversible gate is proposed to minimize the number of reversible gatesand garbage outputs, while designing the reversible BCD arithmetic circuits.

Partial Reversible Gates(PRG) for Reversible BCD Arithmetic