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In this paper, we propose an architecture/methodology for making FPGAssuitable for integer as well as variable precision floating pointmultiplication. The proposed work will of great importance in applicationswhich requires variable precision floating point multiplication such asmulti-media processing applications. In the proposed architecture/methodology,we propose the replacement of existing 18x18 bit and 25x18 bit dedicatedmultipliers in FPGAs with dedicated 24x24 bit and 24x9 bit multipliers,respectively. We have proved that our approach of providing the dedicated 24x24bit and 24x9 bit multipliers in FPGAs will make them efficient for performinginteger as well as single precision, double precision, and Quadruple precisionfloating point multiplications.

Combined Integer and Variable Precision (CIVP) Floating Point Multiplication Architecture for FPGAs