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A 6bit flash-ADC with 1.2GSps, wide analog bandwidth and low power, realizedin a standard digital 0.13 $\mu$m CMOS copper technology is presented.Employing capacitive interpolation gives various advantages when designing forlow power: no need for a reference resistor ladder, implicit sample-and-holdoperation, no edge effects in the interpolation network (as compared toresistive interpolation), and a very low input capacitance of only 400fF, whichleads to an easily drivable analog converter interface. Operating at 1.2GSpsthe ADC achieves an effective resolution bandwidth (ERBW) of 700MHz, whileconsuming 160mW of power. At 600MSps we achieve an ERBW of 600MHz with only90mW power consumption, both from a 1.5V supply. This corresponds tooutstanding Figure-of-Merit numbers (FoM) of 2.2 and 1.5pJ/convstep,respectively. The module area is 0.12mm^2.

A 6bit, 1.2GSps Low-Power Flash-ADC in 0.13$\mu$m Digital CMOS