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This paper presents a design flow for an improved selectivemulti-threshold(Selective-MT) circuit. The Selective-MT circuit is improved sothat plural MT-cells can share one switch transistor. We propose the designmethodology from RTL(Register Transfer Level) to final layout with optimizingswitch transistor structure.

Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction