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Low power oriented circuit optimization consists in selecting the bestalternative between gate sizing, buffer insertion and logic structuretransformation, for satisfying a delay constraint at minimum area cost. In thispaper we used a closed form model of delay in CMOS structures to define metricsfor a deterministic selection of the optimization alternative. The target isdelay constraint satisfaction with minimum area cost. We validate the designspace exploration method, defining maximum and minimum delay bounds on logicalpaths. Then we adapt this method to a "constant sensitivity method" allowing tosize a circuit at minimum area under a delay constraint. An optimisationprotocol is finally defined to manage the trade-off performance constraint -circuit structure. These methods are implemented in an optimization tool (POPS)and validated by comparing on a 0.25$\mu$m process, the optimization efficiencyobtained on various benchmarks (ISCAS?85) to that resulting from an industrialtool.

Low Power Oriented CMOS Circuit Optimization Protocol