English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Global: Zendy Plus annual

Presents the access of premium content as premium feature

Premium Content

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the summarisation as premium feature

Summarisation

Insights

Presents the pdf analysis as premium feature

PDF Analysis

Presents the zaia usage as premium feature

ZAIA

Global: Zendy Plus monthly

Global: Zendy Tools annual

Global: Zendy Tools monthly

Global: Zendy Free Plan

In nanometer scaled CMOS devices significant increase in the subthreshold,the gate and the reverse biased junction band-to-band-tunneling (BTBT) leakage,results in the large increase of total leakage power in a logic circuit.Leakage components interact with each other in device level (through devicegeometry, doping profile) and also in the circuit level (through nodevoltages). Due to the circuit level interaction of the different leakagecomponents, the leakage of a logic gate strongly depends on the circuittopology i.e. number and nature of the other logic gates connected to its inputand output. In this paper, for the first time, we have analyzed loading effecton leakage and proposed a method to accurately estimate the total leakage in alogic circuit, from its logic level description considering the impact ofloading and transistor stacking.

Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits