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We present a complete top-down design of a low-power multi-channel clockrecovery circuit based on gated current-controlled oscillators. The flowincludes several tools and methods used to specify block constraints, to designand verify the topology down to the transistor level, as well as to achieve apower consumption as low as 5mW/Gbit/s. Statistical simulation is used toestimate the achievable bit error rate in presence of phase and frequencyerrors and to prove the feasibility of the concept. VHDL modeling providesextensive verification of the topology. Thermal noise modeling based onwell-known concepts delivers design parameters for the device sizing andbiasing. We present two practical examples of possible design improvementsanalyzed and implemented with this methodology.

Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit