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With the scaling of technology and higher requirements on performance andfunctionality, power dissipation is becoming one of the major designconsiderations in the development of network processors. In this paper, we usean assertion-based methodology for system-level power/performance analysis tostudy two dynamic voltage scaling (DVS) techniques, traffic-based DVS andexecution-based DVS, in a network processor model. Using the automaticallygenerated distribution analyzers, we analyze the power and performancedistributions and study their trade-offs for the two DVS policies withdifferent parameter settings such as threshold values and window sizes. Wediscuss the optimal configurations of the two DVS policies under differentdesign requirements. By a set of experiments, we show that the assertion-basedtrace analysis methodology is an efficient tool that can help a designer easilycompare and study optimal architectural configurations in a large design space.

Assertion-Based Design Exploration of DVS in Network Processor Architectures