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This paper presents a scheme for efficient channel usage between simulatorand accelerator where the accelerator models some RTL sub-blocks in theaccelerator-based hardware/software co-simulation while the simulator runstransaction-level model of the remaining part of the whole chip being verified.With conventional simulation accelerator, evaluations of simulator andaccelerator alternate at every valid simulation time, which results in poorsimulation performance due to startup overhead of simulator-accelerator channelaccess. The startup overhead can be reduced by merging multiple transactions onthe channel into a single burst traffic. We propose a predictive packetizingscheme for reducing channel traffic by merging as many transactions into aburst traffic as possible based on 'prediction and rollback.' Under idealcondition with 100% prediction accuracy, the proposed method shows aperformance gain of 1500% compared to the conventional one.

A Prediction Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation