Leakage Power Minimization using IVC based GSA

The power management has become the major constraint while designing VLSI circuits as parameters like Area, Speed, etc. are critical to be optimized. In this work, a low power 16-bit ALU is designed to perform all arithmetic and logic operations. The present day super computers, mobile gadgets, calculators etc. are using low power ALU systems to perform their tasks. Especially, leakage power occupies major portion of power consumption in the CMOS circuits, as the process technology progresses. The objective of the research work is to reduce leakage power in maximum extent to run the ALU with low power. The proposed model has used IVC based leakage power reduction technique in standby mode by using Gravitational Search Algorithm (GSA). Input Vector Control (IVC) technique is found to be a better alternative in achieving low leakage as it is based on the effect of transistor stacking and it is highly preferred because of its independency over other technological parameters without performance overhead. The GSA locates MLV (Minimum Leakage Vector) in vector combinations of input test circuits of ALU. And then IVC forces the other vector combinations into MLV mode of a test circuit to reduce leakage power. The comparison study has been carried out with Genetic Algorithm (GA) and Particle Swarm Optimization (PSO) algorithm with various test circuits. Power analysis is conducted with GSA to ascertain better leakage reduction and also it locates MLV in less number of iterations. GSA takes only 13 iterations to reach its global space, whereas, PSO takes 62 iterations and GA takes 96 iterations to reach their global space. The simulations are carried out using the Xilinx platform with Verilog coding using PSPICE and MATLAB tools.