Open AccessDesign of a High Speed and Low Power Sample and Hold Circuit for 16 Bit ADC
Author(s) -
Chakradhar Adupa,
Chaithanya Mannepalli,
K. C. Shashidhar,
Srineevasa Rao
Publication year - 2019
Publication title -
international journal of innovative technology and exploring engineering
Language(s) - English
Resource type - Journals
ISSN - 2278-3075
DOI - 10.35940/ijitee.b1056.1292s319
Subject(s) - sample and hold , successive approximation adc , computer science , cmos , electronic engineering , block (permutation group theory) , amplifier , sample (material) , data acquisition , bit (key) , key (lock) , power (physics) , sampling (signal processing) , electrical engineering , data conversion , electronic circuit , computer hardware , telecommunications , engineering , capacitor , mathematics , voltage , physics , geometry , computer security , quantum mechanics , detector , thermodynamics , operating system
Data plays an important role in the present world where the communications are becoming so crucial. Data acquisition and communication systems are in need ofhigherresolution (i.e., 16 Bits)ADCs. The successive approximation (SAR) ADCis suitable for medium to high range resolution applications, the basic building block of the ADC is Sample and hold circuit which will perform a key role in data conversion from analog data to corresponding digital data.In this paper an operational amplifier with gain 96.5 dB and phase margin of 770 with UGB of 12 MHz is designed to implement high speed and low power sample and hold (S/H) circuit using 0.18 µm SCL CMOS Technology, for higher bit ADC applications with sampling frequency of 10 MHz consuming 182 µW power operating at 3.3 V.
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