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Clock Scheme for FPGA Implementation of Globally Asynchronous Locally Synchronous Circuits
Author(s) -
Gouri Wazurkar,
S. L. Badjate
Publication year - 2016
Publication title -
indian journal of science and technology
Language(s) - English
Resource type - Journals
eISSN - 0974-6846
pISSN - 0974-5645
DOI - 10.17485/ijst/2016/v9is1/102358
Subject(s) - clock gating , digital clock manager , computer science , synchronous circuit , clock domain crossing , asynchronous circuit , asynchronous communication , clock skew , asynchronous system , field programmable gate array , cpu multiplier , clock signal , self clocking signal , clock synchronization , synchronizer , embedded system , computer hardware , electronic engineering , synchronization (alternating current) , engineering , computer network , jitter , telecommunications , channel (broadcasting) , distributed computing

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